1. Field of the Invention
The embodiments disclosed herein relate to system performance and, more particularly, to a method, system and computer program product for optimizing system yield (i.e., achieving a target system performance value) based on the results of post-manufacture integrated circuit (IC) chip performance path testing.
2. Description of the Related Art
Currently, performance measurements and, particularly, frequency measurements acquired during performance screen ring oscillator (PSRO) testing are often used to disposition (i.e., screen) integrated circuit (IC) chips at both the wafer-level and the module-level (i.e., the IC chip package-level). For purposes of this disclosure, wafer-level IC chip dispositioning refers to wafer-level performance testing to determine whether IC chips on wafers pass and, thus, are processed into IC chip modules or fail and, thus, are scrapped. Similarly, module-level IC chip dispositioning refers to module-level performance testing to determine whether the IC chip modules pass and, thus, are shipped to customers for incorporation into systems or fail and, thus, are scrapped.
Additionally, a correlation can be made between performance measurements acquired from IC chips during post-manufacture (i.e., wafer-level or module level) PSRO testing and performance measurements taken from systems, which later incorporate the IC chips. This correlation can then be used to adjust a wafer-level or module-level IC chip dispositioning rule in an attempt to improve system yield (i.e., to increase the likelihood that subsequently manufactured systems incorporating the IC chips will meet system performance specifications). Unfortunately, the correlation between post-manufacture PSRO performance measurements and system performance measurements is typically not a very strong correlation and, thus, adjustments to the IC chip dispositioning rule based on this correlation may not improve system yield as predicted.